1. Field of the Invention
The present invention relates to a local exposure method and a local exposure apparatus locally performing exposure processing to a substrate having a photosensitive film formed thereon.
2. Description of the Related Art
In manufacture of, for example, an FPD (Flat Panel Display), a circuit pattern is formed by a so-called photolithography process.
In the photolithography process, a predetermined film is formed on a substrate such as a glass substrate, then a photoresist (hereinafter, called resist) is applied, and preliminary drying processing (reduced-pressure drying and pre-baking processing) vaporizing the solvent in the resist is performed to form a resist film (photosensitive film) as described also in Japanese Laid-open Patent Publication No. 2007-158253. Then, the resist film is exposed according to the circuit pattern and subjected to developing treatment to form a pattern.
In such a photolithography process, it is possible to provide different film thicknesses (a thick film portion R1 and a thin film portion R2) in a resist pattern R as illustrated in FIG. 10A and perform etching treatment a plurality of times using the resist pattern R, thereby reducing the number of photomasks and the number of process steps. Note that such a resist pattern R can be obtained by half (halftone) exposure processing using one halftone mask having portions different in light transmittance.
A circuit pattern forming process when using the resist pattern R to which the half exposure has been applied will be concretely described using FIG. 10A to FIG. 10E.
For example, a gate electrode 200, an insulating layer 201, a Si layer 202 composed of an a-Si layer (non-doped amorphous Si layer) 202a and an n+a-Si layer 202b (phosphor doped amorphous Si layer), and a metal layer 203 for forming an electrode are layered in order on a glass substrate G in FIG. 10A.
Further, a resist film is uniformly formed on the metal layer 203, then the solvent in the resist is vaporized by reduced-pressure drying and pre-baking processing, and then the half exposure processing and developing treatment are performed, whereby a resist pattern R is formed.
After the formation of the resist pattern R (the thick film portion R1 and the thin film portion R2), the metal layer 203 is etched (first etching) is performed using the resist pattern R as a mask as illustrated in FIG. 10B.
Then, ashing processing is performed in plasma to the whole resist pattern R. This forms resist patterns R3 having a film thickness reduced to about half as illustrated in FIG. 10C.
Then, as illustrated in FIG. 10D, etching (second etching) is performed on the exposed metal layer 203 and the Si layer 202 using the resist patterns R3 as a mask, and the resist patterns R3 are finally removed at last as illustrated in FIG. 10E, whereby a circuit pattern is obtained.
However, the half exposure processing using the resist pattern R in which the thick film portion R1 and the thin film portion R2 are formed as described above has a problem. The problem is that when the resist pattern R is formed and its film thickness is ununiform within the substrate, the line width of the pattern to be formed and the pitch between the patterns vary.
Concretely describing the problem using FIG. 11A to FIG. 11E, FIG. 11A illustrates the case where the thin film portion R2 in the resist pattern R is formed such that a thickness t2 thereof is larger than a thickness t1 illustrated in FIG. 10A.
In this case, etching of the metal layer 203 (FIG. 11B) and ashing processing to the whole resist pattern R (FIG. 11C) are performed as in the process illustrated in FIG. 10.
Here, the resist patterns R3 having a film thickness reduced to about half are obtained as illustrated in FIG. 11C, but the thickness of the resist film to be removed is the same as that in the case of FIG. 10C, so that a pitch p2 between a pair of resist patterns R3 illustrated is narrower than a pitch p1 illustrated in FIG. 10C.
Accordingly, the pitch p2 of a circuit pattern obtained through the etching to the metal film 203 and the Si layer 202 (FIG. 11D) and removal of the resist patterns R3 (FIG. 11E) from that state is narrower than the pitch p1 illustrated in FIG. 10E (the line width of the circuit pattern is wider).
To the above problem, means is conventionally taken which specifies a predetermined part in the resist pattern R formed thicker than a desired value by film thickness measurement for each mask pattern through which light is transmitted at exposure processing, and increases the exposure sensitivity at the part.
In the pre-baking processing of heating the resist film before exposure processing to vaporize the solvent, difference is provided in heating amount within the substrate to vary the exposure sensitivity at the predetermined part to thereby adjust a residual film thickness after developing treatment (made uniform within the plane).
Concretely, a heater used for the pre-baking processing is divided into a plurality of areas and the divided heater is independently controlled in drive to thereby perform temperature adjustment for each area.
Further, the heating temperature is adjusted by changing the heights of proximity pins supporting the substrate (changing the distance between the heater and the substrate).